MEMCON and ONFI (Open NAND Flash Interface) http://www.ofni.org

Removing the Page Register Bottleneck

• While the host is reading data from the page register, the next page could be read from the array
• But… there is only one page register…
• The NAND vendors added a cache register to solve this issue

Multiple Plane Operations

• NAND vendors have started splitting the array into “planes” within a die
• Allows simultaneous operations of the same type to different block addresses

Multiple Plane Read Operations

• Multiple plane read operations are when multiple reads are issued at roughly the same time
• Limitation: Page address for reads have to be the same